1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Related Art
In order to broaden the substantial channel width of a transistor without increasing the dimension thereof, there is known a technology of forming concaves and convexes such as trenches in a channel region on a substrate.
For example, Japanese Laid-Open patent publication NOs. H11-103058 and S51-147269 disclose a semiconductor device including a trench gate type transistor in which a trench is formed on the surface of a substrate.
Japanese Laid-Open patent publication NO. 2006-294645 discloses a semiconductor device having: a well region; a plurality of trenches that extend from a surface to a intermediate depth of the well region; a gate insulating film that is disposed on the surface of a concave-convex portion in which the trenches are formed; a gate electrode that is buried inside the trench; and a gate electrode film that is brought into contact with the gate electrode buried inside the trench in the concave-convex region except for areas near both ends of the trench and is disposed on the surface of a substrate; and source and drain regions that are two second conductive-type semiconductor layers having low resistance and are disposed at positions shallower than the depth of the well region, in the well region except for the portion under the gate electrode. Accordingly, since areas near both ends of the trench become the source and drain regions, the contact area between the source and drain regions and the channel region are to be relatively large, whereby the on-resistance can be lowered.
In addition, Japanese Laid-Open patent publication NO. S62-126675 discloses a configuration that is similar to that disclosed in Japanese Laid-Open patent publication NO. 2006-294645.
Meanwhile, although different from the lateral transistors disclosed in Japanese Laid-Open patent publication NOs. H11-103058, S51-147269, 2006-294645, and S62-126675, there is also known a vertical MOS transistor in which the current path is in the vertical direction. Japanese Laid-Open patent publication NO. H6-350090 discloses an insulating-gate field effect device in which a gate conduction material is formed only inside the trench.
Also Japanese Laid-Open patent publication NO. H10-32331 discloses the configuration of a vertical MOS transistor. Here, in the vertical MOS transistor, parasitic capacitance formed by n electric-field relaxing regions and a gate electrode with a gate oxide film interposed therebetween is higher than that of the lateral MOS transistor at the ratio of the chip area, and accordingly, the feedback capacity increases. Therefore, there is a problem in that the switching loss increases. Thus, Japanese Laid-Open patent publication NO. H10-32331 discloses a configuration in which only the film thickness of the gate insulating film in the bottom portion of the trench is formed thick. Accordingly, the switching loss can be reduced by decreasing the parasitic capacitance formed by the n electric-field relaxing regions and the gate electrode while the threshold value of the vertical MOS transistor is maintained to be low.
Also in Japanese Laid-Open patent publication NO. 2009-88188, the configuration of a vertical MOS transistor is disclosed. In the same document, a configuration is disclosed in which, in connection with the trench that is formed in the n-type semiconductor layer, a silicon oxide film having a uniform thickness and being rounded at the corner portion is formed on the bottom portion of trench and the vicinity thereof. On the other hand, on the upper sides of the side faces of the trench, a silicon oxide film that is thinner than the silicon oxide film formed in the bottom portion and the vicinity thereof and is rounded in the corners is formed. The capacitance of the gate decreases due to the thick silicon oxide film, superior characteristics of the transistor are secured through a thin silicon oxide film on the upper portion. In addition, owing to the roundness of the corner portion, a defect in the crystal does not nearly occur, and the electric field of the gate is distributed, whereby the gate breakdown voltage improves.
Japanese Laid-Open patent publication NO. 2007-81396 discloses a MOS transistor including a semiconductor substrate having a principal surface of a (100) face. In addition, a source region and a drain region are disposed on a straight line parallel to the <100> direction.